1. Field of the Invention
The present invention relates to a silicon wafer for deposition of a thin film epitaxial layer formed by a Czochralski method (hereinafter referred to as a CZ method), an epitaxial wafer having an epitaxial layer deposited on it, and a method for manufacturing the same wafers.
2. Description of Related Art
Up to now, an epitaxial wafer has been applied to first a high-performance bipolar transistor and next a bipolar IC. In an epitaxial wafer, since a single silicon crystal epitaxial layer having an arbitrary thickness and resistivity can be formed on a silicon wafer to be a substrate, a high-speed transistor can be realized by forming a high-resistance epitaxial layer on a low-resistance substrate, for example. An effective isolation between pn junction devices which is indispensable to a bipolar IC is effectively performed by forming an epitaxial layer. In recent years, it is demanded to make the thickness of an epitaxial layer as thin as possible in order to make a transistor higher in operating speed and higher in performance.
However, making an epitaxial layer as thin (for example, 3 xcexcm or less) as possible in order to meet this demand causes a problem in case that there is a crystal originated particle (hereinafter referred to as COP) or an interstitial-type large dislocation loop (hereinafter referred to as L/D) on the surface of a silicon wafer to be a substrate. Here, a COP is a defect originated by a crystal that is a kind of a pit. When a mirror-polished silicon wafer is cleaned with a mixed solution of ammonia and hydrogen peroxide, the pit is formed on the silicon wafer. The pit is detected as a particle together with an intrinsic particle by measuring this wafer by means of a particle counter. And an L/D is one of lattice defects of a crystal which is an interstitial-type linear defect which appears as a boundary between a portion slipped and a portion not slipped inside a crystal, and in which partially broken portions of a crystal lattice are linked together in a line. This L/D is called a dislocation cluster, or a dislocation pit since a pit is formed when a silicon wafer having this defect is immersed in a selective etching solution having hydrofluoric acid as a chief ingredient.
That is to say, when there is a COP on the surface of a silicon wafer to be a substrate, a trace of the COP appears on the surface of an epitaxial layer, conforming to the surface shape of this wafer. In case that there is potentially an L/D on the surface of a silicon wafer to be a substrate, the L/D is actualized on the wafer (substrate) under an epitaxial layer by heating of an epitaxial process furnace when the epitaxial layer is formed on this wafer, and this L/D increases the density of defects on the surface of the epitaxial layer.
On the other hand, a CZ silicon wafer may have a ring-shaped oxidation induced stacking fault (hereinafter referred to as OSF) actualized during thermal oxidation in a semiconductor device manufacturing process, depending upon a pulling speed at the time of pulling a single silicon crystal. Oxygen precipitation nuclei to be a bulk micro defect are formed in a crystal during growth of the crystal. The bulk micro defect is formed by actualizing the nuclei in a wafer during heat treatment of the wafer such as an oxidation process when a semiconductor device is manufactured. An OSF is originated by bulk micro defects.
In case that a silicon wafer to be a substrate is a wafer on which OSF appears in such a way, or traces of COP or L/D are actualized on the surface of an epitaxial layer, these OSF, traces of the COP and the like may cause deterioration in electric characteristics, for example, a time dependent dielectric breakdown (TDDB) characteristic, a time zero dielectric breakdown (TZDB) characteristic and the like. Existence of traces of COP or L/D on the surface of an epitaxial layer generates a level difference in a wiring process of a device and this level difference causes breaking of a wire, and thereby degrades yield of product.
In order to solve this problem, a thin film epitaxial wafer and its manufacturing method have been disclosed (Japanese Patent Publication No. 10-209,056 (1998) and Japanese Patent Publication No. 10-209,057 (1998)). Japanese Patent Publication No. 10-209,056 (1998) discloses a method which makes by means of a CZ method a single silicon crystal substrate having a COP density of 1xc3x97105 COPs/cm3 or less and having no COP or a very little number of COPs on the surface of the substrate and forms an epitaxial layer being less than 4.0 xcexcm in thickness on this substrate under a low pressure, and a thin film epitaxial wafer made by this method.
Japanese Patent Publication No. 10-209,057 (1998) discloses a method which makes by means of a CZ method a single silicon crystal substrate being densely doped with a p type impurity and having no COP or a very little number of COPs on the surface of it and forms an epitaxial layer being less than 4.0 xcexcm in thickness on this substrate under a low pressure, and a thin film epitaxial wafer made by this method.
According to these methods, in case of forming an epitaxial layer of 1 xcexcm in thickness for example, it is possible to make 50 or less the number of COPs of 0.13 xcexcm or more on a 6-inch wafer.
However, since both of the two methods described above make a silicon wafer to be a substrate by means of a CZ method from a single silicon crystal pulled at a relatively low speed of about 0.4 mm/minute, they can suppress occurrence of COP in the silicon wafer but result in having L/D generated, and therefore cannot solve the above-mentioned problem that L/D is actualized on the surface of the epitaxial layer.
As shown by solid lines (a) to (c) in FIG. 15, in case that a CZ silicon wafer is a p type wafer doped with B (boron) before the wafer has an epitaxial layer formed on the surface of it, generally the higher the density of oxygen in the wafer is, the higher the density of bulk micro defects (hereinafter referred to as BMD) generated in the wafer by heat treatment in a semiconductor device manufacturing process is. This BMD has a so-called intrinsic gettering (IG) effect of capturing a very small amount of a heavy metal impurity entering during a device manufacturing process.
As shown by dashed and chain lines (d) to (f) in FIG. 15, in case that a CZ silicon wafer is a p type wafer doped with B (boron) after the wafer has an epitaxial layer formed on the surface of it and the density of B of the wafer is less than 1018 atoms/cm3, regardless of whether the density of oxygen is high or low, occurrence of the above-mentioned BMD in the wafer is suppressed and the above-mentioned IG effect is not sufficiently obtained on the other hand, when the density of B of the wafer is 1018 atoms/cm3 or more, the BMD generated as high in density as a wafer before having an epitaxial layer formed on it has an IG effect.
The above-mentioned density of BMD is obtained when a silicon wafer is heat-treated at 750xc2x0 C. for 8 hours and then successively at 1,000xc2x0 C. for 16 hours.
However, in case that a CZ wafer pulled under a condition in which an OSF ring occurs is made to be 1018 atoms/cm3 or more in B density, after an epitaxial layer is formed a problem occurs that BMD is generated higher in density in a location corresponding to the ring than the other locations but BMD is remarkably suppressed to occur outside the OSF ring and thereby the IG effect in the wafer is made ununiform.
A first object of the present invention is to provide a silicon wafer for deposition of an epitaxial layer which is OSF-free and hardly makes traces of COP as well as L/D occur on the surface of the epitaxial layer when the epitaxial layer is formed.
A second object of the present invention is to provide an epitaxial wafer and its manufacturing method in which a uniform IG effect is obtained in the wafer by BMD generated uniformly and densely in the wafer by heat treatment in a semiconductor device manufacturing process after the epitaxial layer is formed.
A third object of the present invention is to provide an epitaxial wafer and its manufacturing method which improve the electric characteristics and bring a large yield in manufacture.
In the first aspect of the present invention, a silicon wafer for deposition of an epitaxial layer, the silicon wafer is 0.02 xcexa9cm or less in resistivity, wherein the number of crystal originated particles (COP) and the number of interstitial-type large dislocation loops (L/D) are respectively 0 to 10 per wafer.
In the second aspect of the present invention, an epitaxial wafer comprises a silicon wafer having no oxidation induced stacking fault (OSF) generated when it is heat-treated in a temperature range of 1000xc2x0 C.xc2x130xc2x0 C. for 2 to 5 hours and then successively in a temperature range of 1130xc2x0 C.xc2x130xc2x0 C. for 1 to 16 hours, and a single silicon crystal epitaxial layer of 0.2 to 5 xcexcm in thickness formed on the silicon wafer, wherein the number of crystal originated particles all over the surface of the epitaxial layer is zero.
In the third aspect of the present invention, an epitaxial wafer manufacturing method comprises the steps of pulling a single silicon ingot, making a silicon wafer by slicing said silicon ingot, and forming a single silicon crystal epitaxial layer on the silicon wafer by means of a chemical vapor deposition method, wherein on the assumption that a pulling speed is V (mm/minute) and a temperature gradient in the axial direction in the center of said ingot is Ga (xc2x0 C. /mm) and a temperature gradient in the axial direction in the periphery of said ingot is Gb (xc2x0 C. /mm) in a temperature range from the melting point of silicon to 1300xc2x0 C., the ingot is pulled so that V/Ga and V/Gb are respectively 0.23 to 0.50 mm2/minutexc2x0 C., and the epitaxial layer is formed with 0.2 to 5 xcexcm in thickness on the surface of the silicon wafer.
In the fourth aspect of the present invention, a silicon wafer is 0.02 xcexa9cm or less in resistivity for deposition of an epitaxial layer, wherein no oxidation induced stacking fault (OSF) appears in the middle part of the silicon wafer when it is heat-treated in a temperature range of 1000xc2x0 C.xc2x130xc2x0 C. for 2 to 5 hours and then successively in a temperature range of 1130xc2x0 C.xc2x130xc2x0 C. for 1 to 16 hours in an oxygen atmosphere.
In the fifth aspect of the present invention, an epitaxial wafer manufacturing method comprises the steps of pulling a single silicon ingot while doping a p-type impurity to a specified or more density, making a silicon wafer by slicing said silicon ingot, and forming a single silicon crystal epitaxial layer on the silicon wafer by means of a chemical vapor deposition method, wherein on the assumption that a pulling speed is V (mm/minute) and a temperature gradient in the axial direction of the ingot is G (xc2x0 C./mm) in a temperature range from the melting point of silicon to 1300xc2x0 C., the ingot is pulled with a specified V/G so that no oxidation induced stacking fault appears in the middle part of said wafer when said wafer is heat-treated in a temperature range of 1000xc2x0 C.xc2x130xc2x0 C. for 2 to 5 hours and then successively in a temperature range of 1130xc2x0 C.xc2x130xc2x0 C. for 1 to 16 hours in an oxygen atmosphere.